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| ht48E30 8-bit i/o type mcu (with eeprom) block diagram rev. 0.00 1 january 12, 2004 general description the ht48E30 is an 8-bit high performance, risc archi - tecture microcontroller device specifically designed for multiple i/o control product applications. the advantages of low power consumption, i/o flexibil- ity, timer functions, oscillator options, halt and wake-up functions, watchdog timer, buzzer driver, as well as low cost, enhance the versatility of these devices to suit a wide range of application possibilities such as industrial control, consumer products, subsystem con- trollers, etc. features operating voltage: f sys =4mhz: 2.2v~5.5v f sys =8mhz: 3.3v~5.5v low voltage reset function 23 bidirectional i/o lines (max.) 1 interrupt input shared with an i/o line 8-bit programmable timer/event counter with overflow interrupt and 8-stage prescaler on-chip crystal and rc oscillator watchdog timer 2048 14 program memory rom (mtp) 128 8 data memory eeprom 96 8 data memory ram buzzer driving pair and pfd supported halt function and wake-up feature reduce power consumption 4-level subroutine nesting up to 0.5 s instruction cycle with 8mhz system clock at v dd =5v bit manipulation instruction 14-bit table read instruction 63 powerful instructions 10 6 erase/write cycles eeprom data memory eeprom data retention > 10 years all instructions in one or two machine cycles in system programming (isp) 24/28-pin skdip/sop package ! ! " ! # # ! $ % & ' ( ) $ $ * ! ! # # ! ! ! # + $ $ ( , # ! # # ! $ - - - ' - ' ' . ' . . / . 0 . 1 . 1 . $ ' $ $ / $ 0 $ ' / 2 & ! ' * preliminary pin assignment pad assignment * the ic substrate should be connected to vss in the pcb layout artwork. ht48E30 rev. 0.00 2 january 12, 2004 preliminary 3 0 4 2 & 5 6 3 0 4 2 5 & 2 4 0 3 6 5 & . 4 . 0 $ & $ 2 $ 4 $ 0 2 & 5 . 2 . & $ 5 $ $ $ . 5 . . . 1 . . 1 & 5 6 3 0 4 2 & 5 5 & 2 4 0 3 6 . 4 . 0 $ & $ 2 $ 4 $ 0 . 2 . & $ 5 $ $ $ . 5 . . . 1 . . 1 7 8 9 2 4 0 3 6 5 5 5 & 2 4 0 3 6 5 & 2 4 0 6 3 & 5 $ 5 $ $ . 5 . . . 1 . . 1 5 & 2 $ 0 $ 4 $ 2 $ & . 0 . 4 . 2 . & $ 5 pad description pad name i/o options description pa0~pa7 i/o pull-high* wake-up cmos/schmitt trigger input bidirectional 8-bit input/output port. each bit can be configured as a wake-up input by options. software instructions determine the cmos output or schmitt trigger or cmos input (depends on options) with pull-high resistor (determined by 1-bit pull-high options). pb0/bz pb1/bz pb2~pb7 i/o pull-high* pb0 or bz pb1 or bz bidirectional 8-bit input/output port. software instructions determine the cmos output or schmitt trigger input with pull-high resistor (deter - mined by pull-high options). the pb0 and pb1 are pin-shared with the bz and bz , respectively. once the pb0 or pb1 is selected as buzzer driving outputs, the output signals come from an internal pfd generator (shared with timer/event counter). vss negative power supply, ground pg0/int i/o pull-high* bidirectional i/o lines. software instructions determine the cmos out - put or schmitt trigger input with pull-high resistor (determined by 1-bit pull-high options). this external interrupt input is pin-shared with pg0. the external interrupt input is activated on a high to low transition. pc0/tmr pc1~pc5 i/o pull-high* bidirectional i/o lines. software instructions determine the cmos out - put or schmitt trigger input with pull-high resistor (determined by 1-bit pull-high options). the timer input are pin-shared with pc0. res i schmitt trigger reset input. active low. vdd positive power supply osc1 osc2 i o crystal or rc osc1and osc2 are connected to an rc network or crystal (deter- mined by options) for the internal system clock. in the case of rc oper- ation, osc2 is the output terminal for 1/4 system clock. note: * the pull-high resistors of each i/o port (pa, pb, pc, pg) are controlled by a 1-bit option. cmos or schmitt trigger option of port a is controlled by a 1-bit option. absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. ht48E30 rev. 0.00 3 january 12, 2004 preliminary d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =4mhz 2.2 5.5 v f sys =8mhz 3.3 5.5 v i dd1 operating current (crystal osc) 3v no load, f sys =4mhz 0.6 1.5 ma 5v 24ma i dd2 operating current (rc osc) 3v no load, f sys =4mhz 0.8 1.5 ma 5v 2.5 4 ma i dd3 operating current (crystal osc) 5v no load, f sys =8mhz 35ma i stb1 standby current (wdt enabled) 3v no load, system halt 5 a 5v 10 a i stb2 standby current (wdt disabled) 3v no load, system halt 1 a 5v 2 a v il1 input low voltage for i/o ports 0 0.3v dd v v ih1 input high voltage for i/o ports 0.7v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v v lvr low voltage reset voltage lvr enabled 2.7 3.0 3.3 v i ol i/o port sink current 3v v ol =0.1v dd 48 ma 5v v ol =0.1v dd 10 20 ma i oh i/o port source current 3v v oh =0.9v dd 2 4 ma 5v v oh =0.9v dd 5 10 ma r ph pull-high resistance 3v 40 60 80 k 5v 10 30 50 k ht48E30 rev. 0.00 4 january 12, 2004 preliminary a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (crystal osc) 2.2v~5.5v 400 4000 khz 3.3v~5.5v 400 8000 khz f sys2 system clock (rc osc) 2.2v~5.5v 400 4000 khz 3.3v~5.5v 400 8000 khz f timer timer i/p frequency (tmr) 2.2v~5.5v 0 4000 khz 3.3v~5.5v 0 8000 khz t wdtosc watchdog oscillator period 3v 45 90 180 s 5v 32 65 130 s t wdt1 watchdog time-out period (wdt osc) 3v without wdt prescaler 11 23 46 ms 5v 8 17 33 ms t wdt2 watchdog time-out period (system clock) without wdt prescaler 1024 t sys t res external reset low pulse width 1 s t sst system start-up timer period wake-up from halt 1024 t sys t int interrupt pulse width 1 s ht48E30 rev. 0.00 5 january 12, 2004 preliminary ht48E30 rev. 0.00 6 january 12, 2004 preliminary functional description execution flow the ht48E30 system clock is derived from either a crystal or an rc oscillator and is internally divided into four non-overlapping clocks. one instruction cycle con - sists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de - coding and execution takes the next instruction cycle. this pipelining scheme ensures that instructions are ef - fectively executed in one cycle. if an instruction changes the contents of the program counter, two cycles are re - quired to complete the instruction. program counter pc the program counter (pc) controls the sequence in which the instructions stored in the program rom are executed and its contents specify a full range of pro - gram memory. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading into the pcl register, subroutine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from interrupt, the pc manip - ulates the program transfer by loading the address cor - responding to each instruction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise proceed with the next instruction. the lower byte of the program counter (pcl) is a read - able and writeable register (06h). moving data into the pcl performs a short jump. the destination will be within the current program rom page. when a control transfer takes place, an additional dummy cycle is required. mode program counter *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 00000000000 external interrupt 00000000100 timer/event counter overflow 00000001000 skip pc+2 loading pcl *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *10~*0: program counter bits s10~s0: stack register bits #10~#0: instruction code bits @7~@0: pcl bits 5 & 5 & 5 & : ! , ' ' 7 9 ; ! ' ' 7 < 9 : ! , ' ' 7 = 9 ; ! ' ' 7 9 : ! , ' ' 7 = 9 ; ! ' ' 7 = 9 = = * ! ' > ' 7 ' * 9 execution flow ht48E30 rev. 0.00 7 january 12, 2004 preliminary instruction table location *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: *10~*0: table location bits p10~p8: current program counter bits @7~@0: table pointer bits in system programming in system programming allows programming and repro - gramming of ht48exx microcontroller on application circuit board, this will save time and money, both during development in the lab. using a simple 3-wire interface, the isp communicates serially with the ht48exx microcontroller, reprogramming program memory and eeprom data memory on the chip. pin name function description pa0 sdata serial data input/output pa4 sclk serial clock input res reset device reset vdd vdd power supply vss vss ground isp pin assignments program memory rom the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organized into 2048 14 bits, addressed by the program counter and ta - ble pointer. certain locations in the program memory are reserved for special usage: location 000h this area is reserved for program initialization. after a chip reset, the program always begins execution at lo - cation 000h. location 004h this area is reserved for the external interrupt service program. if the int input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004h. location 008h this area is reserved for the timer/event counter inter - rupt service program. if a timer interrupt results from a timer/event counter overflow, and if the interrupt is en - abled and the stack is not full, the program begins exe - cution at location 008h. table location any location in the program memory space can be used as look-up tables. the instructions tabrdc [m] (the current page, one page=256 words) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are trans- ferred to the lower portion of tblh, and the remaining 2-bits words are read as 0 . the table higher-order byte register (tblh) is read only. the table pointer (tblp) is a read/write register (07h), which indicates the table location. before accessing the table, the lo- cation must be placed in the tblp. the tblh is read only and cannot be restored. if the main routine and the isr (interrupt service routine) both employ the table read instruction, the contents of the tblh in the main routine are likely to be changed by the table read instruction used in the isr. errors can occur. in other words, using the table read instruction in the main rou - tine and the isr simultaneously should be avoided. however, if the table read instruction has to be applied in both the main routine and the isr, the interrupt is supposed to be disabled prior to the table read in - struction. it will not be enabled until the tblh has been backed up. all table related instructions require 0 : : ? : : ? * ) # ' # ! # # @ ! # ' ; ! ' ! " ! ' a ! # # ) ! ' ! ! " ! ' a ! # ' ( > < " ' a ' 7 2 4 ' b + 9 ( > < " ' a ' 7 2 4 ' b + 9 ! c ' ' ' ' ' ! ' 0 ? 3 ? & ? ? & ' a # ! 0 ? program memory ht48E30 rev. 0.00 8 january 12, 2004 preliminary two cycles to complete the operation. these areas may function as normal program memory depending upon the requirements. stack register stack this is a special part of the memory which is used to save the contents of the program counter (pc) only. the stack is organized into 4 levels and is neither part of the data nor part of the program space, and is neither read - able nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction (ret or reti), the pro - gram counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented (by ret or reti), the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. in a similar case, if the stack is full and a call is sub - sequently executed, stack overflow occurs and the first entry will be lost (only the most recent 4 return ad- dresses are stored). data memory ram the data memory has a capacity of 115 8 bits and is di- vided into two functional groups: special function regis- ters and general purpose data memory (96 8). most are read/write, but some are read only. the special function registers include the indirect ad - dressing registers (r0;00h), timer/event counter (tmr;0dh), timer/event counter control register (tmrc;0eh), program counter lower-order byte regis - ter (pcl;06h), memory pointer registers (mp;01h), ac - cumulator (acc;05h), table pointer (tblp;07h), table higher-order byte register (tblh;08h), status register (status;0ah), interrupt control register (intc;0bh), watchdog timer option setting register (wdts;09h), i/o registers (pa;12h, pb;14h, pc;16h, pg;1eh) and i/o control registers (pac;13h, pbc;15h, pcc;17h, pgc;1fh). the remaining space before the 20h is re - served for future expanded usage and reading these locations will return the result 00h . the general pur - pose data m emory, addressed from 20h to 7fh, is used for data and control information under instruction com - mands. all of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di - rectly. except for some dedicated bits, each bit in the data memory can be set and reset by set [m].i and clr [m].i . they are also indirectly accessible through memory pointer registers (mp). the control register of the eeprom data memory is located at [40h] in bank 1. indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write op - eration on [00h] and [02h] access the ram pointed to by mp0 (01h) and mp1 (03h) respectively. reading lo - cation 00h or 02h indirectly returns the result 00h. while, writing it indirectly leads to no operation. the function of data movement between two indirect ad - dressing registers is not supported. the memory pointer registers, mp0 and mp1, are both 7-bit registers used to access the ram by combining corresponding indirect addressing registers. mp0 can only be applied to data memory in bank 0, while mp1 can be applied to data memory in bank 0 and bank1. ' " $ $ ' 7 6 4 ' . * ! 9 " # ' " $ $ ' ? ? ? 5 ? & ? 2 ? 4 ? 0 ? 3 ? 6 ? $ ? . ? ? ? ? : ? ? ? ? 5 ? & ? 2 ? 4 ? 0 ? 3 ? 6 ? $ ? . ? ? ? ? : ? 0 : ? c ' + + ' ' d d ? + # ! ' $ + + # ' # ! ' + # ! ' $ + + # ' # ! ' . $ ( . ( . ( ? - $ $ $ . . 3 ? : : ? ram mapping ht48E30 rev. 0.00 9 january 12, 2004 preliminary accumulator the accumulator is closely related to alu operations. it is also mapped to location 05h of the data memory and can carry out immediate data operations. the data movement between two data memory locations must pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic opera - tions. the alu provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but also changes the status register. status register status this 8-bit register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). it also records the status information and controls the operation sequence. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addi- tion operations related to the status register may give different results from those intended. the to flag can be affected only by a system power-up, a wdt time-out or executing the clr wdt or halt in- struction. the pdf flag can be affected only by exe- cuting the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on entering the interrupt sequence or exe - cuting the subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status are important and if the subroutine may cor - rupt the status register, precautions must be taken to save it properly. interrupt the device provides an external interrupt and internal timer/event counter interrupts. the interrupt control register (intc;0bh) contains the interrupt control bits to set the enable or disable and the interrupt request flags. once an interrupt subroutine is serviced, all the other in - terrupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may occur during this interval but only the interrupt request flag is recorded. if a certain inter - rupt requires servicing within the service routine, the emi bit and the corresponding bit of the intc may be set to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related in - terrupt is enabled, until the sp is decremented. if immedi - ate service is desired, the stack must be prevented from becoming full. all these kinds of interrupts have a wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro- gram memory. only the program counter is pushed onto the stack. if the contents of the register or status register (status) are altered by the interrupt service program which corrupts the desired control sequence, the con- tents should be saved in advance. external interrupts are triggered by a high to low transi - tion of the int and the related interrupt request flag (eif; bit 4 of intc) will be set. when the interrupt is enabled, the stack is not full and the external interrupt is active, a labels bits function c0 c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac 1 ac is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. z 2 z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. ov 3 ov is set if an operation results in a carry into the highest-order bit but not a carry out of the high - est-order bit, or vice versa; otherwise ov is cleared. pdf 4 pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by ex - ecuting the halt instruction. to 5 to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6 unused bit, read as 0 7 unused bit, read as 0 status register ht48E30 rev. 0.00 10 january 12, 2004 preliminary subroutine call to location 04h will occur. the interrupt request flag (eif) and emi bits will be cleared to disable other interrupts. the internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (tf; bit 5 of intc), caused by a timer overflow. when the interrupt is enabled, the stack is not full and the tf bit is set, a subroutine call to location 08h will occur. the related interrupt request flag (tf) will be reset and the emi bit cleared to disable further interrupts. during the execution of an interrupt subroutine, other in - terrupt acknowledge signals are held until the reti in- struction is executed or the emi bit and the related interrupt control bit are set to 1 (if the stack is not full). to return from the interrupt subroutine, ret or reti may be invoked. reti will set the emi bit to enable an in- terrupt service, but ret will not. interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter- rupts are enabled. in the case of simultaneous requests the following table shows the priority that is applied. these can be masked by resetting the emi bit. no. interrupt source priority vector a external interrupt 1 04h b timer/event counter overflow 2 08h the timer/event counter interrupt request flag (tf), ex - ternal interrupt request flag (eif), enable timer/event counter interrupt bit (eti), enable external interrupt bit (eei) and enable master interrupt bit (emi) constitute an interrupt control register (intc) which is located at 0bh in the data memory. emi, eei, eti are used to control the enabling/disabling of interrupts. these bits prevent the requested interrupt from being serviced. once the interrupt request flags (tf, eif) are set, they will remain in the intc register until the interrupts are serviced or cleared by a software instruction. it is recommended that a program does not use the call subroutine within the interrupt subroutine. in - terrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and enabling the interrupt is not well con trolled, the original control sequence will be dam - aged once the call operates in the interrupt subrou - tine. oscillator configuration there are 2 oscillator circuits in the microcontroller. all of them are designed for system clocks, namely, ex- ternal rc oscillator and external crystal oscillator, which are determined by options. no matter what oscil- lator type is selected, the signal provides the system clock. the halt mode stops the system oscillator and ignores an external signal to conserve power. if an rc oscillator is used, an external resistor between osc1 and vdd is required and the resistance must range from 24k to 1m . the system clock, divided by 4, is available on osc2, which can be used to synchro - nize external logic. the rc oscillator provides the most cost effective solution. however, the frequency of oscil - lation may vary with vdd, temperatures and the chip it - self due to process variations. it is, therefore, not suitable for timing sensitive operations where an accu - rate oscillator frequency is desired. if a crystal oscillator is used, a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator. no other external compo - nents are required. in stead of a crystal, a resonator can also be connected between osc1 and osc2 to obtain a frequency reference, but two external capacitors in osc1 and osc2 are required. the wdt oscillator is a free running on-chip rc oscilla - tor, and no external components are required. even if the system enters the power down mode and the sys - register bit no. label function intc (0bh) 0 emi controls the master (global) interrupt (1= enabled; 0= disabled) 1 eei controls the external interrupt (1= enabled; 0= disabled) 2 eti controls the timer/event counter 0 interrupt (1= enabled; 0= disabled) 3 unused bit, read as 0 4 eif external interrupt request flag (1= active; 0= inactive) 5 tf internal timer/event counter 0 request flag (1= active; 0= inactive) 6 unused bit, read as 0 7 unused bit, read as 0 intc register * ! ' # ! ' # ! ' " ' # & & 0 " : system oscillator ht48E30 rev. 0.00 11 january 12, 2004 preliminary tem clock is stopped, the oscillator still works within a period of 65 s at 5v. the wdt oscillator can be dis - abled by options to conserve power. watchdog timer wdt the wdt clock source is implemented by a dedicated rc oscillator (wdt oscillator), instruction clock (system clock divided by 4), determines the options. this timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. the watchdog timer can be disabled by op - tions. if the watchdog timer is disabled, all the execu - tions related to the wdt result in no operation. once the internal wdt oscillator (rc oscillator with a period of 65 s at 5v normally) is selected, it is first di - vided by 256 (8-stage) to get the nominal time-out pe - riod of 18.6ms at 5v. this time-out period may vary with temperatures, vdd and process variations. by invoking the wdt prescaler, longer time-out periods can be real - ized. writing data to ws2, ws1, ws0 (bit 2,1,0 of the wdts) can give different time-out periods. if ws2, ws1, and ws0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.4s at 5v seconds. if the wdt oscillator is disabled, the wdt clock may still come from the instruction clock and operates in the same manner except that in the halt state the wdt may stop counting and lose its protecting purpose. in this situation the logic can only be restarted by an external logic. the high nibble and bit 3 of the wdts are reserved for user s defined flags, which can be used to indicate some speci- fied status. if the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recom- mended, since the halt will stop the system clock. ws2 ws1 ws0 division ratio 000 1:1 001 1:2 010 1:4 011 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 wdts register the wdt overflow under normal operation will initialize a chip reset and set the status bit to . but in the halt mode, the overflow will initialize a warm reset and only the pc and sp are reset to zero. to clear the contents of wdt (including the wdt prescaler), three methods are adopted; external reset (a low level to res ), software instruction and a halt instruction. the software instruction includes clr wdt and the other set clr wdt1 and clr wdt2 . of these two types of instruction, only one can be active depend - ing on the option clr wdt times selection option .if the clr wdt is selected (i.e. clrwdt times equal one), any execution of the clr wdt instruction will clear the wdt. in the case that clr wdt1 and clr wdt2 are chosen (i.e. clrwdt times equal two), these two instructions must be executed to clear the wdt; otherwise, the wdt may reset the chip as a result of time-out. power down operation halt the halt mode is initialized by the halt instruction and results in the following... the system oscillator will be turned off but the wdt oscillator remains running (if the wdt oscillator is se - lected). the contents of the on chip ram and registers remain unchanged. wdt and wdt prescaler will be cleared and re- counted again (if the wdt clock is from the wdt os- cillator). all of the i/o ports maintain their original status. the pdf flag is set and the to flag is cleared. the system can leave the halt mode by means of an external reset, an interrupt, an external falling edge sig - nal on port a or a wdt overflow. an external reset causes a device initialization and the wdt overflow per - forms a warm reset . after the to and pdf flags are examined, the reason for chip reset can be determined. the pdf flag is cleared by a system power-up or exe - cuting the clr wdt instruction and is set when exe - cuting the halt instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the pc and sp; the others remain in their original status. * ! ' > & 3 < a # ! ' ! - ' 0 < a # ! ' ! 3 < ! < ' - ' # < ! - / - " ! # ! - watchdog timer ht48E30 rev. 0.00 12 january 12, 2004 preliminary the port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each bit in port a can be independently selected to wake up the device by options. awakening from an i/o port stimulus, the program will resume execution of the next instruc - tion. if it awakens from an interrupt, two sequence may occur. if the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. if the interrupt is en - abled and the stack is not full, a regular interrupt re - sponse takes place. if an interrupt request flag is set to 1 before entering the halt mode, the wake-up func - tion of the related interrupt will be disabled. once a wake-up event occurs, it takes 1024 (system clock pe - riod) to resume to normal operation. in other words, a dummy period will be inserted after a wake-up. if the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. if the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the halt status. reset there are three ways in which a reset can occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation the time-out during halt is different from other chip re- set conditions, since it can perform a warm reset that resets only the pc and sp, leaving the other circuits in their original state. some registers remain unchanged during other reset conditions. most registers are reset to the initial condition when the reset conditions are met. by examining the pdf and to flags, the program can distinguish between different chip resets . to pdf reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchanged? to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra delay of 1024 system clock pulses when the sys - tem reset (power-up, wdt time-out or res reset) or the system awakes from the halt state. when a system reset occurs, the sst delay is added during the reset period. any wake-up from halt will en - able an sst delay. an extra option load time delay is added during system reset (power-up, wdt time-out at normal mode or res reset). the functional unit chip reset status are shown below. pc 000h interrupt disable prescaler clear wdt clear. after master reset, wdt begins counting timer/event counter off input/output ports input mode stack pointer, sp points to the top of the stack > > e : f e : f reset circuit note: * make the length of the wiring, which is con - nected to the res pin as short as possible, to avoid noise interference. ! ' # < ! , # " ' ' ! reset timing chart - ' ! - ? $ ( + ! * ! ' ! < a # ! ' # " " ! reset configuration ht48E30 rev. 0.00 13 january 12, 2004 preliminary the registers status is summarized in the following table. register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* tmr xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrc 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu program counter 000h 000h 000h 000h 000h mp -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pc --11 1111 --11 1111 --11 1111 --11 1111 --uu uuuu pcc --11 1111 --11 1111 --11 1111 --11 1111 --uu uuuu pg ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u pgc ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u eecr 1000 ---- 1000 ---- 1000 ---- 1000 ---- uuuu ---- note: * stands for warm reset u stands for unchanged x stands for unknown timer/event counter timer/event counters (tmr) is implemented in the microcontroller. the timer/event counter contains an 8-bit programmable count-up counter and the clock may come from an external source or from the system clock by 4. using the internal clock sources, there are 2 reference time-bases for the timer/event counter. the internal clock source can be selected as coming from f sys or by options. using an external clock input allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base. while using the internal clock allows the user to generate an accu - rate time base. the timer/event counter can generate pfd signals by using external or internal clock and the pfd frequency is determine by the equation f int /[2 (256-n)]. there are 2 registers related to the timer/event counter; tmr ([0dh]), tmrc ([0eh]). two physical registers are mapped to tmr location; writing tmr makes the start - ing value be placed in the timer/event counter preload register and reading tmr retrieves the contents of the timer/event counter. the tmrc is a timer/event counter control register, which defines some options. the tm0, tm1 bits define the operating mode. the event count mode is used to count external events, which means the clock source comes from an external (tmr) pin. the timer mode functions as a normal timer with the clock source coming from the f int clock. the pulse width measurement mode can be used to count the high or low level duration of the external signal (tmr). the counting is based on the f int clock. in the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to ffh. once over - flow occurs, the counter is reloaded from the timer/event counter preload register and generates the interrupt re - quest flag (tf; bit 5 of intc) at the same time. in the pulse width measurement mode with the ton and te bits equal to one, once the tmr has received a tran - sient from low to high (or high to low if the te bits is 0 ) it will start counting until the tmr returns to the original level and resets the ton. the measured result will re - main in the timer/event counter even if the activated transient occurs again. in other words, only one cycle ht48E30 rev. 0.00 14 january 12, 2004 preliminary label (tmrc) bits function psc0~psc2 0~2 defines the prescaler stages, psc2, psc1, psc0= 000: f int =f sys /2 001: f int =f sys /4 010: f int =f sys /8 011: f int =f sys /16 100: f int =f sys /32 101: f int =f sys /64 110: f int =f sys /128 111: f int =f sys /256 te 3 defines the tmr active edge of the timer/event counter 0 (0=active on low to high; 1=active on high to low) ton 4 enable or disable timer 0 counting (0=disabled; 1=enabled) 5 unused bit, read as 0 tm0 tm1 6 7 defines the operating mode 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmrc register ' - # + ! , ! + ' ! # ) ! ' ! + ' # ! # ) ! ! ! ' . + ) b ! ' ! " ! . 1 . 1 3 < ! ' 3 < ' / 7 / 2 4 9 timer/event counter measurement can be done. until setting the ton, the cycle measurement will function again as long as it re - ceives further transient pulse. note that, in this operat - ing mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two modes. to enable the counting operation, the timer on bit (ton; bit 4 of tmrc) should be set to 1. in the pulse width measurement mode, the ton will be cleared au - tomatically after the measurement cycle is completed. but in the other two modes the ton can only be reset by instructions. the overflow of the timer/event counter is one of the wake-up sources. no matter what the opera - tion mode is, writing a 0 to eti can disable the corre - sponding interrupt services. in the case of timer/event counter off condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. but if the timer/event counter is turned on, data written to it will only be kept in the timer/event counter preload register. the timer/event counter will still operate until overflow occurs. when the timer/event counter (reading tmr) is read, the clock will be blocked to avoid errors. as clock blocking may results in a counting error, this must be taken into consideration by the programmer. the bit0~bit2 of the tmrc can be used to define the pre-scaling stages of the internal clock sources of timer/event counter. the definitions are as shown. the overflow signal of the timer/event counter can be used to generate pfd signals for buzzer driving. ht48E30 rev. 0.00 15 january 12, 2004 preliminary input/output ports there are 23 bidirectional input/output lines in the microcontroller, labeled from pa to pc and pg, which are mapped to the data memory of [12h], [14h], [16h] and [1eh] respectively. all of these i/o ports can be used for input and output operations. for input opera - tion, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a,[m] (m=12h, 14h, 16h or 1eh). for output operation, all the data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc, pcc, pgc) to control the input/output configuration. with this control register, cmos output or schmitt trig - ger input with or without pull-high resistor structures can be reconfigured dynamically under software control. to function as an input, the corresponding latch of the con - trol register must write a 1 . the input source also de - pends on the control register. if the control register bit is 1 , the input will read the pad state. if the control regis - ter bit is 0 , the contents of the latches will move to the internal bus. the latter is possible in the read-modify-write instruction. for output function, cmos is the only configuration. these control registers are mapped to locations 13h, 15h, 17h and 1fh. after a chip reset, these input/output lines remain at high levels or floating state (depending on the pull-high op - tions). each bit of these input/output latches can be set or cleared by set [m].i and clr [m].i (m=12h, 14h, 16h or 1eh) instructions. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i , cpl [m] , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability of waking-up the de - vice. the highest 7-bit of port g are not physically imple - mented; on reading them a 0 is returned whereas writing then results in no operation. see application note. there is a pull-high option available for all i/o lines (bit option). once the pull-high option of an i/o line is se - lected, the i/o line has a pull-high resistor. otherwise, the pull-high resistor is absent. it should be noted that a non-pull-high i/o line operating in input mode will cause a floating state. the pb0 and pb1 are pin-shared with bz and bz sig - nals, respectively. if the bz/bz option is selected, the output signal in output mode of pb0/pb1 will be the pfd signal generated by timer/event counter 0 overflow sig- nal. the input mode always remain in its original func- tions. once the bz/bz option is selected, the buzzer output signals are controlled by the pb0 data register only. the i/o functions of pb0/pb1 are shown below. pb0i/o i i oooooooo pb1i/o i o i i iooooo pb0 mode x x c b b c bbbb pb1 mode x c x x x c c c b b pb0 data x x d 0 1 d 0 0101 pb1 data x d x x x d 1 dd x x pb0 pad status i i d 0 b d 0 0b0b pb1 pad status i d i i i d 1 dd0 b note: i input, o output, d, d 0 ,d 1 data, b buzzer option, bz or bz , x don?t care c cmos output ht48E30 rev. 0.00 16 january 12, 2004 preliminary the pg0 is pin-shared with int . it is recommended that unused or not bonded out i/o lines should be set as output pins by software instruction to avoid consuming power under input floating state. low voltage reset lvr the ht48E30 provides a low voltage reset circuit in or- der to monitor the supply voltage of the device. if the supply voltage is within the range 0.9v~v lvr , such as while changing a battery, the lvr will automatically re- set the device internally. the lvr includes the following specifications: within the low voltage range (0.9v~v lvr ), the device remains in their original state until exceeding 1ms. if the low voltage state does not exceed 1ms, the lvr will ignore it and does not perform a reset function. the lvr uses the or function with the external res signal to perform chip reset. the relationship between v dd and v lvr is shown below. note: v opr is the voltage range for proper chip opera - tion at 4mhz system clock. $ / $ 0 . / . 0 / 2 . 1 7 . 8 ' . ' * 9 / 0 ' ' ' * * ! ' - > < " 7 $ ' * 9 + ' ! ' # ! . . 1 . 1 7 . 8 ' . ' * 9 g % g g % g ! ' . # ! ! ' . - # ! ' ! ' # ! , # " ' ! + ' ! ' # ! - # ! ' ! ' # ! ! ' . # ! input/output ports 2 e 2 5 e 5 e & e 6 ( 2 e 2 ht48E30 rev. 0.00 17 january 12, 2004 preliminary eeprom data memory the 128 8 bits eeprom data memory is readable and writable during normal operation. it is indirectly addressed through the control register eecr ([40h] in bank 1). the eecr can be read and written to only by indirect addressing mode using mp1. label (eecr) bits function 0~3 unused bit, read as 0 cs 4 eeprom data memory select sk 5 serial clock input to eeprom data memory di 6 serial data input to eeprom data memory do 7 serial data output from eeprom data memory 2 e 2 ( e 6 ! ' # ! f f ' " ! # ! ( ' ! ! ' ! low voltage reset note: *1: to make sure that the system oscillator has stabilized, the sst provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: since low voltage has to be maintained in its original state until exceeding 1ms, therefore after a 1ms delay, the device enters a reset mode. % ! ( # + > ! $ + + ' # ! % ' ' ? 6 5 ( & 4 ! # ! $ + + ' + * ' ' $ * % c ' 7 3 3 9 ! " ! ' . eeprom data memory block diagram ht48E30 rev. 0.00 18 january 12, 2004 preliminary the eeprom data memory is accessed via a three-wire serial communication interface by writing to eecr. it is arranged into 128 words by 8 bits. the eeprom data memory contains seven instructions: read, erase, write, ewen, ewds, eral and wral. these instructions are all made up of 10 bits data: 1 start bit, 2 op-code bits and 7 address bits. by writing cs, sk and di, these instructions can be given to the eeprom. these serial instruction data pre - sented at the di will be written into the eeprom data memory at the rising edge of sk. during the read cy - cle, do acts as the data output and during the write or erase cycle, do indicates the busy/ready status. when the do is active for read data or as a busy/ ready indicator the cs pin must be high; otherwise do will be in a high state. for successful instructions, cs must be low once after the instruction is sent. after power on, the device is by default in the ewds state. and, an ewen instruction must be performed before any erase or write instruction can be executed. % ! ! ! ? ! % ( ! % ? ! ! ? ! ! # + ' ! # + ' ! the following are the functional descriptions and timing diagrams of all seven instructions. eecr a.c. characteristics ta=25 c symbol parameter v cc =5v 10% v cc =2.2v 10% unit min. max. min. max. f sk clock frequency 0201mhz t skh sk high time 250 500 ns t skl sk low time 250 500 ns t css cs setup time 50 100 ns t csh cs hold time 0 0 ns t cds cs deselect time 250 250 ns t dis di setup time 100 200 ns t dih di hold time 100 200 ns t pd1 do delay to 1 250 500 ns t pd0 do delay to 0 250 500 ns t sv status valid time 250 250 ns t hz do disable time 100 200 ns t pr write cycle time per word 2 5ms ht48E30 rev. 0.00 19 january 12, 2004 preliminary read the read instruction will stream out data at a specified address on the do. the data on do changes during the low-to-high edge of sk. the 8 bits data stream is pre - ceded by a logical 0 dummy bit. irrespective of the condition of the ewen or ewds instruction, the read command is always valid and independent of these two instructions. after the data word has been read the in - ternal address will be automatically incremented by 1 al - lowing the next consecutive data word to be read out without entering further address data. the address will wrap around with cs high until cs returns to low. ewen/ewds the ewen/ewds instruction will enable or disable the programming capabilities. at both the power on and power off state the device automatically entered the dis - able mode. before a write, erase, wral or eral in - struction is given, the programming enable instruction ewen must be issued, otherwise the erase/write in - struction is invalid. after the ewen instruction is issued, the programming enable condition remains until power is turned off or an ewds instruction is given. no data can be written into the eeprom data memory in the program - ming disabled state. by so doing, the internal memory data can be protected. erase the erase instruction erases data at the specified ad- dresses in the programming enable mode. after the erase op-code and the specified address have been issued, the data erase is activated by the falling edge of cs. since the internal auto-timing generator provides all timing signals for the internal erase, so the sk clock is not required. during the internal erase, we can verify the busy/ready status if cs is high. the do will remain low but when the operation is over, the do will return to high and further instructions can be executed. write the write instruction writes data into the eeprom data memory at the specified addresses in the program - ming enable mode. after the write op-code and the specified address and data have been issued, the data writing is activated by the falling edge of cs. since the internal auto-timing generator provides all timing signal for the internal writing, so the sk clock is not required. the auto-timing write cycle includes an automatic erase-before-write capability. so, it is not necessary to erase data before the write instruction. during the in - ternal writing, we can verify the busy/ready status if cs is high. the do will remain low but when the operation is over, the do will return to high and further instructions can be executed. eral the eral instruction erases the entire 128 8 memory cells to a logical 1 state in the programming enable mode. after the erase-all instruction set has been is - sued, the data erase feature is activated by the falling edge of cs. since the internal auto-timing generator provides all timing signal for the erase-all operation, so the sk clock is not required. during the internal erase-all operation, we can verify the busy/ready status if cs is high. the do will remain low but when the operation is over, the do will return to high and further instruction can be executed. wral the wral instruction writes data into the entire 128 8 memory cells in the programming enable mode. after the write-all instruction set has been issued, the data writing is activated by the falling edge of cs. since the internal auto-timing generator provides all timing signals for the write-all operation, so the sk clock is not re - quired. during the internal write-all operation, we can verify the busy/ready status if cs is high. the do will re - main low but when the operation is over the do will re - turn to high and further instruction can be executed. eecr control timing diagrams read % ! ! ' a # ! 7 9 ! f f ' $ + + ' " # ! ' ! ! # * ' * ' ! ' ! , ' ; ! ' b + $ $ + $ 7 3 9 $ 4 0 ht48E30 rev. 0.00 20 january 12, 2004 preliminary ewen /ewds write erase eral % ! + a * 7 9 ! ! ' a # ! h - h - % ! + a * 7 9 ! ! ! . * + * # * ! ! ' a # ! $ $ < $ < $ $ % ! + a * 7 9 ! ! ! . * + * # * ! ! ' a # ! $ $ < $ < $ $ % ! + a * 7 9 ! ! ! . * + * # * ! ! ' a # ! ht48E30 rev. 0.00 21 january 12, 2004 preliminary wral eeprom data memory instruction set summary instruction comments start bit op code address data read read data 1 10 a6~a0 d7~d0 erase erase data 1 11 a6~a0 write write data 1 01 a6~a0 d7~d0 ewen erase/write enable 1 00 11xxxxx ewds erase/write disable 1 00 00xxxxx eral erase all 1 00 10xxxxx wral write all 1 00 01xxxxx d7~d0 note: x stands for don t care options the following table shows all kinds of options in the microcontroller. all of the options must be defined to ensure proper system functioning. items options 1 wdt clock source: wdt oscillator or f sys /4 or disable 2 clrwdt instructions: 1 or 2 instructions 3 timer/event counter clock source: f sys 4 pa bit wake-up enable or disable 5 pa cmos or schmitt input 6 pa, pb, pc, pg pull-high enable or disable (by port) 7 bz/bz enable or disable 8 lvr enable or disable 9 system oscillator: rc or crystal % ! + a * 7 9 ! ! ! . * + * # * ! ! ' a # ! application circuits the following table shows the c1, c2 and r1 value according different crystal values. crystal or resonator c1, c2 r1 4mhz crystal 0pf 10k 4mhz resonator (3 pin) 0pf 12k 4mhz resonator (2 pin) 10pf 12k 3.58mhz crystal 0pf 10k 3.58mhz resonator (2 pin) 25pf 10k 2mhz crystal & resonator (2 pin) 25pf 10k 1mhz crystal 35pf 27k 480khz resonator 300pf 9.1k 455khz resonator 300pf 10k 429khz resonator 300pf 10k note: the resistance and capacitance for reset circuit should be designed in such a way as to ensure that the vdd is stable and remains within a valid operating voltage range before bringing res to high. * make the length of the wiring, which is connected to the res pin as short as possible, to avoid noise interference. ht48E30 rev. 0.00 22 january 12, 2004 preliminary # # ! e : f > e : e : f > $ / $ 0 . / . 0 / 2 . . 1 . . 1 : ' ! , ' ) 8 ' ! a ' a b & > i i & 0 " : ' " ' + # ! " # instruction set summary mnemonic description instruction cycle flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry and result in data memory decimal adjust acc for addition with result in data memory 1 1 (1) 1 1 1 (1) 1 1 1 (1) 1 1 (1) 1 (1) z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 (1) 1 (1) 1 (1) 1 1 1 1 (1) 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 (1) 1 1 (1) z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 (1) 1 1 (1) 1 1 (1) 1 1 (1) none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 (1) 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 (1) 1 (1) none none ht48E30 rev. 0.00 23 january 12, 2004 preliminary mnemonic description instruction cycle flag affected branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 (2) 1 (2) 1 (2) 1 (2) 1 (3) 1 (3) 1 (2) 1 (2) 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read rom code (current page) to data memory and tblh read rom code (last page) to data memory and tblh 2 (1) 2 (1) none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 (1) 1 (1) 1 1 1 1 (1) 1 1 none none none to,pdf to (4) ,pdf (4) to (4) ,pdf (4) none none to,pdf note: x: immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address : flag is affected : flag is not affected (1) : if a loading to the pcl register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : if a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). otherwise the original instruction cycle is unchanged. (3) : (1) and (2) (4) : the flags may be affected by the execution status. if the watchdog timer is cleared by executing the clr wdt1 or clr wdt2 instruction, the to and pdf are cleared. otherwise the to and pdf flags remain unchanged. ht48E30 rev. 0.00 24 january 12, 2004 preliminary instruction definition adc a,[m] add data memory and carry to the accumulator description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the accumulator. operation acc acc+[m]+c affected flag(s) to pdf ov z ac c adcm a,[m] add the accumulator and carry to data memory description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the specified data memory. operation [m] acc+[m]+c affected flag(s) to pdf ov z ac c add a,[m] add data memory to the accumulator description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc+[m] affected flag(s) to pdf ov z ac c add a,x add immediate data to the accumulator description the contents of the accumulator and the specified data are added, leaving the result in the accumulator. operation acc acc+x affected flag(s) to pdf ov z ac c addm a,[m] add the accumulator to the data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the data memory. operation [m] acc+[m] affected flag(s) to pdf ov z ac c ht48E30 rev. 0.00 25 january 12, 2004 preliminary and a,[m] logical and accumulator with data memory description data in the accumulator and the specified data memory perform a bitwise logical_and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) to pdf ov z ac c and a,x logical and immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) to pdf ov z ac c andm a,[m] logical and data memory with the accumulator description data in the specified data memory and the accumulator perform a bitwise logical_and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) to pdf ov z ac c call addr subroutine call description the instruction unconditionally calls a subroutine located at the indicated address. the program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. the indicated address is then loaded. program execution continues with the instruction at this address. operation stack pc+1 pc addr affected flag(s) to pdf ov z ac c clr [m] clear data memory description the contents of the specified data memory are cleared to 0. operation [m] 00h affected flag(s) to pdf ov z ac c ht48E30 rev. 0.00 26 january 12, 2004 preliminary clr [m].i clear bit of data memory description the bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) to pdf ov z ac c clr wdt clear watchdog timer description the wdt is cleared (clears the wdt). the power down bit (pdf) and time-out bit (to) are cleared. operation wdt 00h pdf and to 0 affected flag(s) to pdf ov z ac c 00 clr wdt1 preclear watchdog timer description together with clr wdt2, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction just sets the indicated flag which im - plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt 00h* pdf and to 0* affected flag(s) to pdf ov z ac c 0* 0* clr wdt2 preclear watchdog timer description together with clr wdt1, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction, sets the indicated flag which im- plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt 00h* pdf and to 0* affected flag(s) to pdf ov z ac c 0* 0* cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice-versa. operation [m] [m ] affected flag(s) to pdf ov z ac c ht48E30 rev. 0.00 27 january 12, 2004 preliminary cpla [m] complement data memory and place result in the accumulator description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice-versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m ] affected flag(s) to pdf ov z ac c daa [m] decimal-adjust accumulator for addition description the accumulator value is adjusted to the bcd (binary coded decimal) code. the accumu - lator is divided into two nibbles. each nibble is adjusted to the bcd code and an internal carry (ac1) will be done if the low nibble of the accumulator is greater than 9. the bcd ad - justment is done by adding 6 to the original value if the original value is greater than 9 or a carry (ac or c) is set; otherwise the original value remains unchanged. the result is stored in the data memory and only the carry flag (c) may be affected. operation if acc.3~acc.0 >9 or ac=1 then [m].3~[m].0 (acc.3~acc.0)+6, ac1=ac else [m].3~[m].0 (acc.3~acc.0), ac1=0 and if acc.7~acc.4+ac1 >9 or c=1 then [m].7~[m].4 acc.7~acc.4+6+ac1,c=1 else [m].7~[m].4 acc.7~acc.4+ac1,c=c affected flag(s) to pdf ov z ac c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) to pdf ov z ac c deca [m] decrement data memory and place result in the accumulator description data in the specified data memory is decremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) to pdf ov z ac c ht48E30 rev. 0.00 28 january 12, 2004 preliminary halt enter power down mode description this instruction stops program execution and turns off the system clock. the contents of the ram and registers are retained. the wdt and prescaler are cleared. the power down bit (pdf) is set and the wdt time-out bit (to) is cleared. operation pc pc+1 pdf 1 to 0 affected flag(s) to pdf ov z ac c 01 inc [m] increment data memory description data in the specified data memory is incremented by 1 operation [m] [m]+1 affected flag(s) to pdf ov z ac c inca [m] increment data memory and place result in the accumulator description data in the specified data memory is incremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) to pdf ov z ac c jmp addr directly jump description the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. operation pc addr affected flag(s) to pdf ov z ac c mov a,[m] move data memory to the accumulator description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) to pdf ov z ac c ht48E30 rev. 0.00 29 january 12, 2004 preliminary mov a,x move immediate data to the accumulator description the 8-bit data specified by the code is loaded into the accumulator. operation acc x affected flag(s) to pdf ov z ac c mov [m],a move the accumulator to data memory description the contents of the accumulator are copied to the specified data memory (one of the data memories). operation [m] acc affected flag(s) to pdf ov z ac c nop no operation description no operation is performed. execution continues with the next instruction. operation pc pc+1 affected flag(s) to pdf ov z ac c or a,[m] logical or accumulator with data memory description data in the accumulator and the specified data memory (one of the data memories) per- form a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) to pdf ov z ac c or a,x logical or immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or x affected flag(s) to pdf ov z ac c orm a,[m] logical or data memory with the accumulator description data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_or operation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) to pdf ov z ac c ht48E30 rev. 0.00 30 january 12, 2004 preliminary ret return from subroutine description the program counter is restored from the stack. this is a 2-cycle instruction. operation pc stack affected flag(s) to pdf ov z ac c ret a,x return and place immediate data in the accumulator description the program counter is restored from the stack and the accumulator loaded with the speci - fied 8-bit immediate data. operation pc stack acc x affected flag(s) to pdf ov z ac c reti return from interrupt description the program counter is restored from the stack, and interrupts are enabled by setting the emi bit. emi is the enable master (global) interrupt bit. operation pc stack emi 1 affected flag(s) to pdf ov z ac c rl [m] rotate data memory left description the contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 affected flag(s) to pdf ov z ac c rla [m] rotate data memory left and place result in the accumulator description data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 [m].7 affected flag(s) to pdf ov z ac c ht48E30 rev. 0.00 31 january 12, 2004 preliminary rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated 1 bit left. bit 7 re - places the carry bit; the original carry flag is rotated into the bit 0 position. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 c c [m].7 affected flag(s) to pdf ov z ac c rlca [m] rotate left through carry and place result in the accumulator description data in the specified data memory and the carry flag are rotated 1 bit left. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. the rotated result is stored in the accumulator but the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 c c [m].7 affected flag(s) to pdf ov z ac c rr [m] rotate data memory right description the contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 affected flag(s) to pdf ov z ac c rra [m] rotate right and place result in the accumulator description data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 [m].0 affected flag(s) to pdf ov z ac c rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are together rotated 1 bit right. bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 c c [m].0 affected flag(s) to pdf ov z ac c ht48E30 rev. 0.00 32 january 12, 2004 preliminary rrca [m] rotate right through carry and place result in the accumulator description data of the specified data memory and the carry flag are rotated 1 bit right. bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. the rotated result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 c c [m].0 affected flag(s) to pdf ov z ac c sbc a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+c affected flag(s) to pdf ov z ac c sbcm a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+c affected flag(s) to pdf ov z ac c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, [m] ([m] 1) affected flag(s) to pdf ov z ac c sdza [m] decrement data memory and place result in acc, skip if 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. the result is stored in the accumulator but the data memory remains unchanged. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy - cles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, acc ([m] 1) affected flag(s) to pdf ov z ac c ht48E30 rev. 0.00 33 january 12, 2004 preliminary set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) to pdf ov z ac c set [m]. i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) to pdf ov z ac c siz [m] skip if increment data memory is 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the fol - lowing instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, [m] ([m]+1) affected flag(s) to pdf ov z ac c siza [m] increment data memory and place result in acc, skip if 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the next instruction is skipped and the result is stored in the accumulator. the data memory re- mains unchanged. if the result is 0, the following instruction, fetched during the current in- struction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, acc ([m]+1) affected flag(s) to pdf ov z ac c snz [m].i skip if bit i of the data memory is not 0 description if bit i of the specified data memory is not 0, the next instruction is skipped. if bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). other - wise proceed with the next instruction (1 cycle). operation skip if [m].i 0 affected flag(s) to pdf ov z ac c ht48E30 rev. 0.00 34 january 12, 2004 preliminary sub a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+1 affected flag(s) to pdf ov z ac c subm a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+1 affected flag(s) to pdf ov z ac c sub a,x subtract immediate data from the accumulator description the immediate data specified by the code is subtracted from the contents of the accumula - tor, leaving the result in the accumulator. operation acc acc+x +1 affected flag(s) to pdf ov z ac c swap [m] swap nibbles within the data memory description the low-order and high-order nibbles of the specified data memory (1 of the data memo- ries) are interchanged. operation [m].3~[m].0 [m].7~[m].4 affected flag(s) to pdf ov z ac c swapa [m] swap data memory and place result in the accumulator description the low-order and high-order nibbles of the specified data memory are interchanged, writ - ing the result to the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected flag(s) to pdf ov z ac c ht48E30 rev. 0.00 35 january 12, 2004 preliminary sz [m] skip if data memory is 0 description if the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c sza [m] move data memory to acc, skip if 0 description the contents of the specified data memory are copied to the accumulator. if the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c sz [m].i skip if bit i of the data memory is 0 description if bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m].i=0 affected flag(s) to pdf ov z ac c tabrdc [m] move the rom code (current page) to tblh and data memory description the low byte of rom code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) to pdf ov z ac c tabrdl [m] move the rom code (last page) to tblh and data memory description the low byte of rom code (last page) addressed by the table pointer (tblp) is moved to the data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) to pdf ov z ac c ht48E30 rev. 0.00 36 january 12, 2004 preliminary xor a,[m] logical xor accumulator with data memory description data in the accumulator and the indicated data memory perform a bitwise logical exclu - sive_or operation and the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) to pdf ov z ac c xorm a,[m] logical xor data memory with the accumulator description data in the indicated data memory and the accumulator perform a bitwise logical exclu - sive_or operation. the result is stored in the data memory. the 0 flag is affected. operation [m] acc xor [m] affected flag(s) to pdf ov z ac c xor a,x logical xor immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical exclusive_or op - eration. the result is stored in the accumulator. the 0 flag is affected. operation acc acc xor x affected flag(s) to pdf ov z ac c ht48E30 rev. 0.00 37 january 12, 2004 preliminary package information 24-pin skdip (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 1235 1265 b 255 265 c 125 135 d 125 145 e16 20 f50 70 g 100 h 295 315 i 345 360 0 15 ht48E30 rev. 0.00 38 january 12, 2004 preliminary & 5 $ . : ? 28-pin skdip (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 1375 1395 b 278 298 c 125 135 d 125 145 e16 20 f50 70 g 100 h 295 315 i 330 375 0 15 ht48E30 rev. 0.00 39 january 12, 2004 preliminary ' ' 3 2 & $ . : ? 24-pin sop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 394 419 b 290 300 c14 20 c 590 614 d92 104 e 50 f4 g32 38 h4 12 0 10 ht48E30 rev. 0.00 40 january 12, 2004 preliminary & 5 $ . : j ? 28-pin sop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 394 419 b 290 300 c14 20 c 697 713 d92 104 e 50 f4 g32 38 h4 12 0 10 ht48E30 rev. 0.00 41 january 12, 2004 preliminary 3 2 & $ . : j ? product tape and reel specifications reel dimensions sop 24w symbol description dimensions in mm a reel outer diameter 330 1.0 b reel inner diameter 62 1.5 c spindle hole diameter 13.0+0.5 0.2 d key slit width 2.0 0.5 t1 space between flange 24.8+0.3 0.2 t2 reel thickness 30.2 0.2 sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330 1.0 b reel inner diameter 62 1.5 c spindle hole diameter 13.0+0.5 0.2 d key slit width 2.0 0.5 t1 space between flange 24.8+0.3 0.2 t2 reel thickness 30.2 0.2 ht48E30 rev. 0.00 42 january 12, 2004 preliminary $ . carrier tape dimensions sop 24w symbol description dimensions in mm w carrier tape width 24.0 0.3 p cavity pitch 12.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.55+0.1 d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.9 0.1 b0 cavity width 15.9 0.1 k0 cavity depth 3.1 0.1 t carrier tape thickness 0.35 0.05 c cover tape width 21.3 sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.0 0.3 p cavity pitch 12.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5+0.1 d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.85 0.1 b0 cavity width 18.34 0.1 k0 cavity depth 2.97 0.1 t carrier tape thickness 0.35 0.01 c cover tape width 21.3 ht48E30 rev. 0.00 43 january 12, 2004 preliminary - : ! % . $ ht48E30 rev. 0.00 44 january 12, 2004 preliminary copyright 2004 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor (shanghai) inc. 7th floor, building 2, no.889, yi shan rd., shanghai, china tel: 021-6485-5560 fax: 021-6485-0313 http://www.holtek.com.cn holtek semiconductor (hong kong) ltd. block a, 3/f, tin on industrial building, 777-779 cheung sha wan rd., kowloon, hong kong tel: 852-2-745-8288 fax: 852-2-742-8657 holmate semiconductor, inc. 46712 fremont blvd., fremont, ca 94538 tel: 510-252-9880 fax: 510-252-9885 http://www.holmate.com |
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